1. Field of the Invention
The present invention generally relates to modulators, and more particularly to a system and method for encoding an input data stream by utilizing a predictive, look-ahead feature to modify the output in anticipation of large changes in the input.
2. Discussion of the Related Art
Delta encoders and sigma-delta encoders are well known devices that are used to convert a multi-valued sequence of data points into a binary stream of bits. FIGS. 1A and 1B are block diagrams that illustrate a first-order delta encoder and a first-order sigma-delta encoder, respectively. Although the two different types of encoders are implemented differently, their overall function is similar, and is well known by persons skilled in the art.
As illustrated in FIG. 1A, a delta encoder includes a comparator 10 and an integrator 15 configured as shown. An input signal 17 is provided to one input of the comparator 10, while the second input 19 of the comparator 10 is obtained from the output of the integrator 15. Generally, the integrator 15 is configured so that its output 20 attempts to track the output of the comparator 10. As is further known, delta encoders may be implemented in hardware, software, or a combination of the two. If implemented in software, a pseudo-code representation for the operation of a delta encoder may be as follows:
BEGIN
Initialize Variables
STEP=1
Read input value into IVAL
Compare with running integral (INTEG)
If (IVAL greater than =INTEG),
then BIT=STEP,
else BIT=xe2x88x92STEP
Increment INTEG by BIT
END.
In the above listing, the variable xe2x80x9cSTEPxe2x80x9d defines the step size of the integrator 15. The larger the step size, the more quickly the integrator 15 may respond to changes in its input.
FIG. 1A also illustrates an integrator 16 that may be disposed within a decoder for receiving the compressed bit stream 21, after it has been communicated across a channel 22. In this configuration, the output of integrator 16 should closely match the output 20 of integrator 15. In this regard, and as is known, the integrated value of the bitstream output is a reasonably close estimate of the input stream (neglecting a possible DC offset).
For completeness, reference is made briefly to FIG. 1B, which is a block diagram illustrating a sigma-delta encoder. Like the delta encoder, the sigma-delta encoder operates to conduct a multi-valued sequence of data points into a binary stream of bits. A sigma-delta encoder is implemented with a summer (or adder) 32, an integrator 25 and a comparator 30, configured as shown in FIG. 1B. The output 40 is inverted at 42 and added to the input 27 by the adder 32. In this way, the output of the adder 32 is representative of an error signal (e.g., differential) between the input 27 and the output 40. This differential or error signal is fed to the integrator 25, which operates to track changes in the error signal. The output of the integrator 25 is then compared to zero by the comparator 30. As is known, the average value of the bitstream output is a reasonably close estimate of the input stream.
As should be understood, the output 40 is a compressed bit stream. A low-pass filter 34 may be disposed within a decoder to receive the compressed bit stream 40, after the bit stream 40 is communicated across a channel 36. The low-pass filter 34 operates to decode the received signal to recover, in essence, a signal that closely matches the input stream 27.
Hereinafter, the discussion will focus on delta encoders. However, it should be understood that the inventive concepts and features apply equally sigma-delta encoders as well.
Reference is now made to FIGS. 2A-2B, which are graphs illustrating the output of a delta encoder operating in accordance with the pseudo-code listing above, where the integrator 15 operates with a step size of 1. Referring first to FIG. 2A, an input signal 46 is shown having an irregular, step waveform defined by level, but changing values. In the illustrated example, the input stream begins at an amplitude near 100, then falls to an amplitude of slightly below zero, then to an amplitude of slightly less than xe2x88x9250, before rising to an amplitude of nearly +50. The output signal 48 is shown to significantly lag behind the input signal, where there are rapid changes in the input signal. As will be understood by persons skilled in the art, with the step size of one, the xe2x80x9cslopexe2x80x9d of the output signal will be a xe2x80x9c1xe2x80x9d unit voltage change per unit time (e.g., +45 degrees or xe2x88x9245 degrees, if the graph uses the same linear distance on they axis to represent a step voltage that it uses to represent a step in time). In regions like the region designated by reference numeral 50, where the output signal approximately equals the input signal, the output signal oscillates above and below the level of the input signal. The oscillations appear as noise, and the amplitude of the oscillations is equal to the step size.
In FIG. 2B, an input signal 56 is in the form of a sinusoidal waveform, of increasing frequency. As shown, the output signal 58 tracks the input signal, again having a substantial lag time between the output signal and the input signal.
Reference is now made to FIGS. 3A and 3B, which are graphs illustrating the operation of a delta encoder having a step size of 8. It should be noted that the graphs and waveforms set forth in the drawings are intended only to be illustrative of certain concepts, may not be accurately depicted to scale. The input waveforms 46 and 56 in FIGS. 3A and 3B are the same as those illustrated in FIGS. 2A and 2B. As illustrated, however, the output signals 58 and 68 respond much more quickly to changes in the input signals, due to the larger step size, However, in regions (like region 52) where the output is substantially the same as the input, a much larger amplitude of noise is observed. In order to obtain the benefits of large and small step sizes, delta encoders (and sigma-delta encoders) have been known to be configured with an adaptive step size. Encoders with adaptive step sizes dynamically adjust the operation of the integrator 15 based upon the differential between the input and output signals. An algorithm (pseudo-code) for a software implementation for such a system is provided immediately below (text following xe2x80x9c#xe2x80x9d is comment, and not part of pseudo-code).
BEGIN
Initialize Variables
EXPON=1.6 #an exponential increment
SAME=0
Read input value into IVAL
Compare with running integral (INTEG)
If (IVAL greater than =INTEG),
then BIT=1,
else BIT=xe2x88x921
If (BITOLD=BIT)
Then SAME=SAME+1 #could limit to max of 8
Else if (SAME greater than =2), then SAME=SAMExe2x88x922
Increment INTEG by BIT*(EXPON){circumflex over ( )}SAME
BITOLD=BIT
END.
In the algorithm presented above, the step size is increased as the output continues to trail the input for successive integrations. Graphs illustrating the operations of an encoder having an adaptive step size are illustrated in FIGS. 4A and 4B. Specifically, the graphs in FIGS. 4A and 4B having input signals 46 and 56 that are the same as the input signals of FIGS. 2 and 3 as is illustrated, illustrate the operation of a delta encoder having an adaptive step size that aggressively tracks the input signal. However, as large, rapid changes are made in the input signal, the output signal causally lags the input. Although the output catches up quickly due to the adaptive step size, it is always late to respond. In certain applications, such as video applications, the use of such an encoder to encode the video signal will result in a shearing of the left-hand edge of highly contrasting objects in the video frame.
Accordingly, there is a desire to provide an encoder having a faster response to large changes in an input data stream.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve certain advantages and novel features, the present invention is generally directed to a system and method for encoding an input signal stream. In accordance with one aspect of the invention, a method operates to compare an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The method then stores a plurality of successive binary values from the comparing step. Thereafter, the method simulates an integration function for a plurality of possible bit sequences of the plurality of successive binary values. Then, the method determines which sequence results in the smallest error between the input signal stream and the output value of the integration function. Finally, the method uses the most significant bit of the determined sequence to adjust the integration function.
In accordance with one embodiment of the invention, the integration function is simulated for a plurality of possible bit sequences includes simulating an integration function for all possible bit sequences. In another embodiment, the method operates to determine which sequence results in the smallest error by calculating a root mean square (RMS) error value of the output value of the integration function and the input value. In the preferred embodiment, the method adaptively adjusts the step size of the integration function based upon successive values of the most significant bit of the determined sequence.
In accordance with another aspect of the invention, an encoder is provided for encoding an input signal stream. The encoder includes a comparator configured to compare an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The encoder further includes a memory configured to store a plurality of successive binary values from the comparator, and means for simulating an integration function for a plurality of possible bit sequences of the plurality of successive binary values. The comparator further includes means for determining which sequence results in the smallest error between the input signal stream and the output value of the integration function, and means for adjusting the integration function based upon the most significant bit of the determined sequence.
It should be appreciated that the various means elements may be implemented in hardware, software, or a combination of the two. In the preferred embodiment, the various means elements are predominately implemented in software.